Search Results

Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems

Authors: Purohit, Sohan; Lanuzza, Marco; Perri, Stefania; Corsonello, Pasquale; Margala, Martin

Source: Journal of Low Power Electronics, Volume 5, Number 3, October 2009 , pp. 326-338(13)

Publisher: American Scientific Publishers

Adaptive real-time image processing exploiting two dimensional reconfigurable architecture

Authors: Braun, Lars; Göhringer, Diana; Perschke, Thomas; Schatz, Volker; Hübner, Michael; Becker, Jürgen

Source: Journal of Real-Time Image Processing, Volume 4, Number 2, June 2009 , pp. 109-125(17)

Publisher: Springer

ERP II systems to support dynamic, reconfigurable and agile Virtual Enterprises

Authors: Ponis, Stavros T.; Spanos, Athanasios C.

Source: International Journal of Applied Systemic Studies, Volume 2, Number 3, 6 August 2009 , pp. 265-283(19)

Publisher: Inderscience Publishers

Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures

Authors: Kissler, Dmitrij; Strawetz, Andreas; Hannig, Frank; Teich, Jürgen

Source: Journal of Low Power Electronics, Volume 5, Number 1, April 2009 , pp. 96-105(10)

Publisher: American Scientific Publishers

A component-based policy-neutral architecture for kernel-level access control

Authors: Lacoste, Marc; Jarboui, Tahar; He, Ruan

Source: annals of telecommunications - annales des télécommunications, Volume 64, Numbers 1-2, February 2009 , pp. 121-146(26)

Publisher: Springer

A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs

Authors: Siozios, Kostas; Soudris, Dimitrios

Source: Journal of Low Power Electronics, Volume 4, Number 3, December 2008 , pp. 275-289(15)

Publisher: American Scientific Publishers

Proposal of synthesisable analogue-to-digital converters from VHDL-AMS

Authors: Domenech-Asensi, G.; Garrigos-Guerrero, J.

Source: International Journal of Electronics, Volume 95, Number 9, January 2008 , pp. 891-902(12)

Publisher: Taylor and Francis Ltd

Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures

Authors: Lee, Jong Eun; Choi, Kiyoung; Dutt, Nikil

Source: International Journal of Embedded Systems, Volume 3, Number 3, 14 September 2008 , pp. 119-127(9)

Publisher: Inderscience Publishers

MT-ADRES: multi-threading on coarse-grained reconfigurable architecture

Authors: Wu, Kehuai; Kanstein, Andreas; Madsen, Jan; Berekovic, Mladen

Source: International Journal of Electronics, Volume 95, Number 7, July 2008 , pp. 761-776(16)

Publisher: Taylor and Francis Ltd

Real-time human action recognition on an embedded, reconfigurable video processing architecture

Authors: Meng, Hongying; Freeman, Michael; Pears, Nick; Bailey, Chris

Source: Journal of Real-Time Image Processing, Volume 3, Number 3, September 2008 , pp. 163-176(14)

Publisher: Springer

Model-based mapping of reconfigurable image registration on FPGA platforms

Authors: Sen, Mainak; Hemaraj, Yashwanth; Plishker, William; Shekhar, Raj; Bhattacharyya, Shuvra

Source: Journal of Real-Time Image Processing, Volume 3, Number 3, September 2008 , pp. 149-162(14)

Publisher: Springer

ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing

Authors: Saponara, Sergio; Casula, Michele; Fanucci, Luca

Source: Journal of Real-Time Image Processing, Volume 3, Number 3, September 2008 , pp. 201-216(16)

Publisher: Springer

The Architecture and Development Flow of the S5 Software Configurable Processor

Author: Arnold, Jeffrey

Source: The Journal of VLSI Signal Processing, Volume 47, Number 1, April 2007 , pp. 3-14(12)

Publisher: Springer

Small-scale reconfigurability for improved performance and double-precision in graphics hardware

Source: International Journal of Electronics, Volume 94, Number 5, May 2007 , pp. 549-561(13)

Publisher: Taylor and Francis Ltd

A flexible processor for the characteristic 3 &#951;<SUB align=right>T pairing

Authors: Ronan, Robert; Murphy, Colin; Kerins, Tim; O.hEigeartaigh, Colm; Barreto, Paulo S.L.M.

Source: International Journal of High Performance Systems Architecture, Volume 1, Number 2, 14 October 2007 , pp. 79-88(10)

Publisher: Inderscience Publishers

Compact FPGA-based systolic array architecture suitable for vision systems

Authors: Saldana, Griselda; Arias-Estrada, Miguel

Source: International Journal of High Performance Systems Architecture, Volume 1, Number 2, 14 October 2007 , pp. 124-132(9)

Publisher: Inderscience Publishers

Reconfigurable hardware for neural networks: binary versus stochastic

Authors: Nedjah, Nadia; Macedo Mourelle, Luiza

Source: Neural Computing & Applications, Volume 16, Number 3, May 2007 , pp. 249-255(7)

Publisher: Springer

Fine grain pipeline systems for real-time motion and stereo-vision computation

Authors: Diaz, Javier; Ros, Eduardo; Prieto, Alberto; Pelayo, Francisco J.

Source: International Journal of High Performance Systems Architecture, Volume 1, Number 1, 19 April 2007 , pp. 60-68(9)

Publisher: Inderscience Publishers

Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture

Authors: Dimitroulakos, Grigoris; Galanis, Michalis; Goutis, Costas

Source: The Journal of Supercomputing, Volume 40, Number 2, May 2007 , pp. 127-157(31)

Publisher: Springer

Using model engineering for the criticality analysis of reconfigurable manufacturing systems architectures

Authors: Lamotte, Florent Frizon De; Berruet, Pascal; Philippe, Jean-Luc

Source: International Journal of Manufacturing Technology and Management, Volume 11, Numbers 3-4, 20 April 2007 , pp. 315-337(23)

Publisher: Inderscience Publishers