Search Results

Fast and accurate power estimation of FPGA DSP components based on high-level switching activity models

Authors: Jevtic, Ruzica; Carreras, Carlos; Caffarena, Gabriel

Source: International Journal of Electronics, Volume 95, Number 7, July 2008 , pp. 653-668(16)

Publisher: Taylor and Francis Ltd

Scalable and Systolic Architecture for Computing Double Exponentiation Over GF(2 ^m )

Authors: Lee, Chiou-Yng; Lin, Jim-Min; Chiou, Che

Source: Acta Applicandae Mathematicae, Volume 93, Numbers 1-3, September 2006 , pp. 161-178(18)

Publisher: Springer

Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power Applications

Authors: Navarro-Botello, Victor; Montiel-Nelson, Juan A.; Nooshabadi, Saeid

Source: Journal of Low Power Electronics, Volume 2, Number 2, August 2006 , pp. 300-307(8)

Publisher: American Scientific Publishers

Performance exploration of adder architectures for small to moderate-sized low-power, high-performance adders

Authors: Gupta, Anu; Shekhar, Chandra

Source: Microelectronics International, Volume 22, Number 3, 2005 , pp. 20-27(8)

Publisher: Emerald Group Publishing Limited

VLSI design investigation for low-cost, low-power FFT/IFFT processing in advanced VDSL transceivers

Authors: Saponara S.; Fanucci L.

Source: Microelectronics Journal, Volume 34, Number 2, 1 February 2003 , pp. 133-148(16)

Publisher: Elsevier

Energy Efficient Adiabatic Multiplier-Accumulator Design

Authors: Suvakovic D.; Salama C.A.T.

Source: The Journal of VLSI Signal Processing, Volume 33, Numbers 1-2, January 2003 , pp. 83-103(21)

Publisher: Springer

Single flux quantum one-decimal-digit RNS adder

Authors: Vukovic N.; Feldman M.J.

Source: Applied Superconductivity, Volume 6, Number 10, 11 October 1999 , pp. 609-614(6)

Publisher: Elsevier

Low-voltage adders for power-efficient arithmetic circuits

Author: Margala M.

Source: Microelectronics Journal, Volume 30, Number 12, December 1999 , pp. 1241-1247(7)

Publisher: Elsevier

A comparative study of CMOS circuit design styles for low-power high-speed VLSI circuits

Authors: Bisdounis L.; Gouvetas D.; Koufopavlou O.

Source: International Journal of Electronics, Volume 84, Number 6, 1 June 1998 , pp. 599-613(15)

Publisher: Taylor and Francis Ltd

Design and Evaluation of Adiabatic Arithmetic Units

Authors: Knapp M.C.; Kindlmann P.J.; Papaefthymiou M.C.

Source: Analog Integrated Circuits and Signal Processing, Volume 14, Numbers 1-2, September 1997 , pp. 71-79(9)

Publisher: Springer