Search Results

A Parallel and Randomized Algorithm for Large-Scale Discrete Dual-Vt Assignment and Continuous Gate Sizing

Authors: Wu, Tai-Hsuan; Xie, Lin; Davoodi, Azadeh

Source: Journal of Low Power Electronics, Volume 4, Number 2, August 2008 , pp. 191-201(11)

Publisher: American Scientific Publishers

Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory

Authors: Bhardwaj, Sarvesh; Vrudhula, Sarma

Source: Journal of Low Power Electronics, Volume 4, Number 1, April 2008 , pp. 68-80(13)

Publisher: American Scientific Publishers

Modeling leakage power reduction in VLSI as optimization problems

Authors: Wang, Wenxin; Areibi, Shawki; Anis, Mohab

Source: Optimization and Engineering, Volume 8, Number 2, June 2007 , pp. 129-162(34)

Publisher: Springer

Optimizing performances of switched current memory cells through a heuristic

Authors: Fakhfakh, Mourad; Loulou, Mourad; Masmoudi, Nouri

Source: Analog Integrated Circuits and Signal Processing, Volume 50, Number 2, February 2007 , pp. 115-126(12)

Publisher: Springer

Gate Sizing and V_t Assignment for Active-Mode Leakage Power Reduction

Authors: Gao, Feng; Hayes, John P.

Source: Journal of Low Power Electronics, Volume 2, Number 2, August 2006 , pp. 230-239(10)

Publisher: American Scientific Publishers

Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, and Threshold Voltage Selection

Authors: Bhardwaj, Sarvesh; Cao, Yu; Vrudhula, Sarma

Source: Journal of Low Power Electronics, Volume 2, Number 2, August 2006 , pp. 240-250(11)

Publisher: American Scientific Publishers

Transistor Sizing of Logic Gates to Maximize Input Delay Variability

Authors: Raja, Tezaswi; Agrawal, Vishwani D.; Bushnell, Michael L.

Source: Journal of Low Power Electronics, Volume 2, Number 1, April 2006 , pp. 121-128(8)

Publisher: American Scientific Publishers

Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design

Authors: Binkley, D.; Blalock, B.; Rochelle, J.

Source: Analog Integrated Circuits and Signal Processing, Volume 47, Number 2, May 2006 , pp. 137-163(27)

Publisher: Springer

Minimizing Spurious Switching Activities with Transistor Sizing

Authors: Wróblewski A.; Schimpfle C.V.; Schumacher O.; Nossek J.A.

Source: VLSI Design, Volume 15, Number 2, 1 January 2002 , pp. 537-545(9)

Publisher: Taylor and Francis Ltd

Performance analysis of tapered gate in PD/SOI CMOS technology

Authors: Hwang W.; Chuang C. T.; Curran B. W.; Rosenfield M. G.

Source: International Journal of Electronics, Volume 89, Number 4, 1 April 2002 , pp. 267-275(9)

Publisher: Taylor and Francis Ltd

VLSI Circuit Performance Optimization by Geometric Programming

Authors: Chu C.; Wong D.F.

Source: Annals of Operations Research, Volume 105, Numbers 1-4, July 2001 , pp. 37-60(24)

Publisher: Springer

POPS: A tool for delay/power performance optimization

Authors: Azemard N.; Auvergne D.

Source: Journal of Systems Architecture, Volume 47, Number 3, April 2001 , pp. 375-382(8)

Publisher: Elsevier

Combinatorial cell design for CMOS libraries

Authors: Beeftink F.; Kudva P.; Kung D.S.; Puri R.; Stok L.

Source: Integration, the VLSI Journal, Volume 29, Number 1, March 2000 , pp. 67-93(27)

Publisher: Elsevier

Simulation of the Drain-Current Characteristics of MOSFETs with Ultrathin Oxides in the Presence of Direct Tunneling

Authors: Shiely J.P.; Massoud H.Z.

Source: Microelectronic Engineering, Volume 48, Number 1, September 1999 , pp. 101-104(4)

Publisher: Elsevier

Timing driven cell replication during placement for cycle time optimization

Authors: Neumann I.; Post H.-U.

Source: Integration, the VLSI Journal, Volume 27, Number 2, July 1999 , pp. 131-141(11)

Publisher: Elsevier

A Flexible DSP-based Network for Real-Time Co-operative Windowing Applications

Authors: Nassif S.C.; Capson D.W.

Source: Real-Time Imaging, Volume 3, Number 4, August 1997 , pp. 283-293(11)

Publisher: Elsevier

Useful-Skew Clock Routing with Gate Sizing for Low Power Design

Authors: Xi J.G.; Dai W.W-M.

Source: The Journal of VLSI Signal Processing, Volume 16, Numbers 2-3, 19 June 1997 , pp. 163-179(17)

Publisher: Springer

Low frequency annular transducers for detecting and characterizing microemboli in cardiopulmonary bypass (CPB) flow circuits with the embolus to blood power ratio (EBR)

Authors: Moehring M.A.; Spencer M.P.; Radford R.L.; McDaniel M.D.; Mattson G.A.

Source: European Journal of Ultrasound, Volume 5, Supplement 1, May 1997 , pp. 41-41(1)

Publisher: Elsevier

A Flexible DSP-based Network for Real-Time Co-operative Windowing Applications

Authors: Nassif S.C.; Capson D.W.

Source: Real-Time Imaging, Volume 3, Number 4, August 1997 , pp. 283-293(11)

Publisher: Academic Press

Performance optimization of VLSI interconnect layout

Authors: Cong J.; Lei H.; Cheng-Kok K.; Madden P.H.

Source: Integration, the VLSI Journal, Volume 21, Number 1, November 1996 , pp. 1-94(94)

Publisher: Elsevier