Search Results

On-chip implementation of multiprocessor networks and switch fabrics

Authors: Ye, Terry Tao; Micheli, Giovanni De

Source: International Journal of Embedded Systems, Volume 3, Number 4, 3 January 2009 , pp. 209-218(10)

Publisher: Inderscience Publishers

VLSI floorplan repair using dynamic white-space management, constraint graphs, and linear programming

Authors: Vorwerk, Kristoffer; Kennings, Andrew; Anjos, Miguel

Source: Engineering Optimization, Volume 40, Number 6, June 2008 , pp. 559-577(19)

Publisher: Taylor and Francis Ltd

Simulated Annealing Based Temperature Aware Floorplanning

Authors: Han, Yongkui; Koren, Israel

Source: Journal of Low Power Electronics, Volume 3, Number 2, August 2007 , pp. 141-155(15)

Publisher: American Scientific Publishers

Performance and low power driven floorplanning

Authors: Xu, Ning; Jiang, Zhoughua; Huang, Feng

Source: Journal of Algorithms & Computational Technology, Volume 1, Number 2, June 2007 , pp. 161-169(9)

Publisher: Multi-Science Publishing Co Ltd

Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design

Authors: Xie, Yuan; Hung, Wei-lun

Source: The Journal of VLSI Signal Processing, Volume 45, Number 3, December 2006 , pp. 177-189(13)

Publisher: Springer

Temperature-Aware Floorplanning of 3-D ICs Considering Thermally Dependent Leakage Power

Authors: Deng, Yangdong; Li, Peng

Source: Journal of Low Power Electronics, Volume 2, Number 2, August 2006 , pp. 177-188(12)

Publisher: American Scientific Publishers

Early Quality Assessment for Low Power Behavioral Synthesis

Authors: Kursun, Eren; Mukherjee, Rajarshi; Memik, Seda Ogrenci

Source: Journal of Low Power Electronics, Volume 1, Number 3, December 2005 , pp. 273-285(13)

Publisher: American Scientific Publishers

Microarchitecture Level Interconnect Modeling Considering Layout Optimization

Authors: Liao, Weiping; He, Lei

Source: Journal of Low Power Electronics, Volume 1, Number 3, December 2005 , pp. 297-308(12)

Publisher: American Scientific Publishers

Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-Cell Placement

Authors: Alupoaei S.; Katkoori S.

Source: The Journal of VLSI Signal Processing, Volume 37, Number 1, May 2004 , pp. 151-163(13)

Publisher: Springer

Guided Local Search for Final Placement in VLSI Design

Authors: Faroe O.; Pisinger D.; Zachariasen M.

Source: Journal of Heuristics, Volume 9, Number 3, June 2003 , pp. 269-295(27)

Publisher: Springer

ViSta: a tool suite for the visualization of behavioral requirements

Authors: Castello R.; Mili R.; Tollis I.G.

Source: Journal of Systems and Software, Volume 62, Number 3, 15 June 2002 , pp. 141-159(19)

Publisher: Elsevier

On the approximability of two tree drawing conventions

Author: Penna P.

Source: Information Processing Letters, Volume 82, Number 5, 15 June 2002 , pp. 237-242(6)

Publisher: Elsevier

Floorplanning with abutment constraints based on corner block list

Authors: Ma Y.; Hong X.; Dong S.; Cai Y.; Cheng C.-K.; Gu J.

Source: Integration, the VLSI Journal, Volume 31, Number 1, November 2001 , pp. 65-77(13)

Publisher: Elsevier

3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems

Authors: Bazargan K.; Kastner R.; Sarrafzadeh M.

Source: Design Automation for Embedded Systems, Volume 5, Numbers 3-4, August 2000 , pp. 329-338(10)

Publisher: Springer

Integration of retiming with architectural floorplanning

Authors: Tabbara A.; Tabbara B.; Brayton R.K.; Newton A.R.

Source: Integration, the VLSI Journal, Volume 29, Number 1, March 2000 , pp. 25-43(19)

Publisher: Elsevier

A GA with heuristic-based decoder for IC floorplanning - A Guide to the Theory of NP-Completeness

Authors: Gwee B.H.; Lim M.H.

Source: Integration, the VLSI Journal, Volume 28, Number 2, January 1999 , pp. 157-172(16)

Publisher: Elsevier

A timing-driven floorplanning algorithm with the Elmore delay model for building block layout

Authors: Koide T.; Wakabayashi S.

Source: Integration, the VLSI Journal, Volume 27, Number 1, 1 January 1999 , pp. 57-76(20)

Publisher: Elsevier

Rectangular grid drawings of plane graphs

Authors: Rahman M.S.; Nakano S.-i.; Nishizeki T.

Source: Computational Geometry, Volume 10, Number 3, June 1998 , pp. 203-220(18)

Publisher: Elsevier

An interactive and integrated thermal characterization of component placement on a printed circuit board

Authors: Blanchard J.-L.; Louage S.

Source: Microelectronics Journal, Volume 28, Number 3, March 1997 , pp. 209-219(11)

Publisher: Elsevier