Search Results

Energy-Aware Compilation for Embedded Processors with Technology Scaling Considerations

Authors: Huang, Po-Kuan; Ghiasi, Soheil

Source: Journal of Low Power Electronics, Volume 5, Number 4, December 2009 , pp. 439-453(15)

Publisher: American Scientific Publishers

Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels

Authors: Wang, Weihuang; Kim, Euncheol; Gunnam, Kiran K.; Choi, Gwan S.

Source: Journal of Low Power Electronics, Volume 5, Number 3, October 2009 , pp. 303-312(10)

Publisher: American Scientific Publishers

Temperature Aware Scheduling for Embedded Processors

Authors: Jayaseelan, Ramkumar; Mitra, Tulika

Source: Journal of Low Power Electronics, Volume 5, Number 3, October 2009 , pp. 363-372(10)

Publisher: American Scientific Publishers

A Workload Based Lookup Table for Minimal Power Operation Under Supply and Body Bias Control

Authors: Sreejith, K.; Amrutur, Bharadwaj; Balivada, Ashok

Source: Journal of Low Power Electronics, Volume 5, Number 2, August 2009 , pp. 173-184(12)

Publisher: American Scientific Publishers

Optimal two-level speed assignment for real-time systems

Authors: Bini, Enrico; Scordino, Claudio

Source: International Journal of Embedded Systems, Volume 4, Number 2, 20 August 2009 , pp. 101-111(11)

Publisher: Inderscience Publishers

LD-DVS: load-aware dual-speed dynamic voltage scaling

Authors: Poellabauer, Christian; Rajan, Dinesh; Zuck, Russell

Source: International Journal of Embedded Systems, Volume 4, Number 2, 20 August 2009 , pp. 112-126(15)

Publisher: Inderscience Publishers

Fixed-priority scheduling to reduce both the dynamic and leakage energy on variable voltage processors

Authors: Quan, Gang; Niu, Linwei; Mochocki, Bren; Hu, Xiaobo S.

Source: International Journal of Embedded Systems, Volume 4, Number 2, 20 August 2009 , pp. 127-140(14)

Publisher: Inderscience Publishers

SYS-EDF: a system-wide energy-efficient scheduling algorithm for hard real-time systems

Authors: Cheng, Hui; Goddard, Steve

Source: International Journal of Embedded Systems, Volume 4, Number 2, 20 August 2009 , pp. 141-151(11)

Publisher: Inderscience Publishers

Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks

Authors: Viraraghavan, Janakiraman; Amrutur, Bharadwaj; Visvanathan, V.

Source: Journal of Low Power Electronics, Volume 4, Number 3, December 2008 , pp. 301-319(19)

Publisher: American Scientific Publishers

Performance Analysis of Voltage-Scaled Static and Dynamic CMOS Circuits

Authors: Chandel, Rajeevan; Nataraj, Y.; Khanna, Gargi

Source: Journal of Nanoelectronics and Optoelectronics, Volume 3, Number 2, July 2008 , pp. 171-176(6)

Publisher: American Scientific Publishers

Energy-Aware Task Scheduling and Dynamic Voltage Scaling in a Real-Time System

Authors: Rong, Peng; Pedram, Massoud

Source: Journal of Low Power Electronics, Volume 4, Number 1, April 2008 , pp. 1-10(10)

Publisher: American Scientific Publishers

Design and Analysis of a Low Power Multi-Threshold CMOS Based ARM926 System

Authors: Idgunji, Sachin; Flynn, David

Source: Journal of Low Power Electronics, Volume 4, Number 1, April 2008 , pp. 48-59(12)

Publisher: American Scientific Publishers

A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction

Authors: Devanathan, V.R.; Ravikumar, C.P.; Mehrotra, Rajat; Kamakoti, V.

Source: Journal of Low Power Electronics, Volume 4, Number 1, April 2008 , pp. 101-110(10)

Publisher: American Scientific Publishers

Exploring Very Low-Energy Logic: A Case Study

Authors: Alarcón, L.P.; Liu, T.T.; Pierson, M.D.; Rabaey, J.M.

Source: Journal of Low Power Electronics, Volume 3, Number 3, December 2007 , pp. 223-233(11)

Publisher: American Scientific Publishers

Low Power and Energy Efficient Asynchronous Design

Authors: Beerel, Peter A.; Roncken, Marly E.

Source: Journal of Low Power Electronics, Volume 3, Number 3, December 2007 , pp. 234-253(20)

Publisher: American Scientific Publishers

A new way of estimating compute-boundedness and its application to dynamic voltage scaling

Authors: Venkatachalam, Vasanth; Franz, Michael; Probst, Christian W.

Source: International Journal of Embedded Systems, Volume 3, Numbers 1-2, 2 December 2007 , pp. 17-30(14)

Publisher: Inderscience Publishers

Reducing energy consumption of parallel sparse matrix applications through integrated link/CPU voltage scaling

Authors: Son, Seung; Malkowski, Konrad; Chen, Guilin; Kandemir, Mahmut; Raghavan, Padma

Source: The Journal of Supercomputing, Volume 41, Number 3, September 2007 , pp. 179-213(35)

Publisher: Springer

Evaluation of an Adaptive Dynamic Voltage Scaling Scheme for Hard Real-Time Applications

Authors: Dolwin, Craig A.; Yassine, Hatem

Source: Journal of Low Power Electronics, Volume 3, Number 2, August 2007 , pp. 217-221(5)

Publisher: American Scientific Publishers

Feedback fuzzy-DVS scheduling of control tasks

Authors: Jin, Hong; Wang, Danli; Wang, Hongan; Wang, Hui

Source: The Journal of Supercomputing, Volume 41, Number 2, August 2007 , pp. 147-162(16)

Publisher: Springer

Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiproceesor DSP

Authors: Qiu, Meikang; Jia, Zhiping; Xue, Chun; Shao, Zili; Sha, Edwin

Source: The Journal of VLSI Signal Processing, Volume 46, Number 1, January 2007 , pp. 55-73(19)

Publisher: Springer