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2 articles with title/keywords/abstract containing DUAL-RAIL ENCODING

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Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design

Authors: Di, Jia; Yuan, J.S.

Source: Journal of Low Power Electronics, Volume 2, Number 2, August 2006 , pp. 201-216(16)

Publisher: American Scientific Publishers

Delay-insensitive gate-level pipelining

Authors: Smith S.C.; DeMara R.F.; Yuan J.S.; Hagedorn M.; Ferguson D.

Source: Integration, the VLSI Journal, Volume 30, Number 2, October 2001 , pp. 103-131(29)

Publisher: Elsevier

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