Low Voltage and Low Power Pulse Flip-Flops in Nanometer CMOS Processes

This paper presents a low power channel-length biasing pulse flip-flop (CLBPFF) aimed at a substantial reduction in leakage power. The proposed CLBPFF has been compared with the transmission gate flip-flop (TGFF) and the hybrid latch flip-flop (HLFF) in term of power dissipation, delay and energy delay product (EDP). Voltage scaling for the proposed CLBPFF has also been carried out. All flip-flops are simulated using a 45nm CMOS technology by varying supply voltage from 1.1V to 0.6V with 0.1V steps. Taken as an example, a practical sequential system realized with the proposed flip-flop is demonstrated using a mode-5 counter. The simulation results demonstrate that the proposed CLBPFF achieves considerable total power and leakage power reductions compared with HLFF and TGFF. Moreover, the results show that lowering supply voltage is advantageous, especially in medium-voltage region (0.8V-0.9V), which yields the best EDP for the proposed CLBPFF.