Low-Voltage Low-Power CMOS RF Four-Quadrant Multiplier

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Abstract:



This paper describes a CMOS four-quadrant multiplier intended for use in the front-end receiver by utilizing the square-law characteristic of the MOS transistor in the saturation region. The circuit was simulated in standard 0.5 μm CMOS level 3 MOSIS (BSIM3 SPICE-based). The mixer has a third-order inter modulation (IM3) of 34.7 dBmV, a third-order intercept point (IP3) of -5.7 dBm, 1-dB compression (P-1dB) of -10.4 dBm and the power consumption is 1.18 mW from a single 1.5 V power supply. One of the features of the proposed design is using two MOS transistors limitation to reduce the supply voltage, which leads to reduce the power consumption.

Keywords: Front-End; GPS; GSM; RF-Mixer; WLAN

Document Type: Miscellaneous

DOI: http://dx.doi.org/10.1078/1434-8411-54100143

Affiliations: Faculty of Engineering, Electronics and Communication Engineering Department, Cairo University, Cairo, Egypt. Fax: +202-5723486, E-mail: asoliman@idsc.net.eg

Publication date: January 1, 2003

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