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Automated Robust Design and Optimization of Integrated Circuits by Means of Penalty Functions

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The ever-shorter time-to-market calls for efficient robust IC design algorithms. Robust circuits satisfy all design requirements across a range of operating conditions and manufacturing process variations. In the paper we propose an automated robust IC design and optimization process derived from the design algorithms utilized manually by experienced analog IC designers. We achieve this by transforming the robust design and optimization problem into a constrained optimization problem using tradeoff planes and penalty functions. We illustrate the method on a robust differential amplifier design problem. Circuits resulting from several different optimization runs show that a computer can not only improve existing circuit designs but it can also size a circuit with very little initial knowledge. The resulting circuits have comparable or even superior performance to humanly designed circuits. The method could easily take advantage of parallel processing but is still efficient enough to be run on a single computer.

Keywords: Analog IC; CAD; Circuit sizing; Optimization; Penalty function

Document Type: Original Article


Affiliations: University of Ljubljana, Faculty of Electrical Engineering, Tržaška cesta 25, SI-1000 Ljubljana, Slovenia. E-mail:

Publication date: 2003-01-01

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