Abstract:

A new speed-up method of lock up time is proposed for the phase locked loop (PLL) frequency synthesizer in the local oscillation circuit of a radio receiver. Doubling of reference frequency is achieved by using a new (N + 1/2) programmable divider which enables a half division ratio, compared with that of a conventional divider, and it leads to a bigger loop gain K and the speed-up of lock up time. The experimental results of lock up time will be given together with the spectrum of the output frequency.

Language: English

Document Type: Research article