@article {Sumi:1 February 1998:0020-7217:123,
	author = "Sumi Y.",
	author = "Obote S.",
	author = "Tsuda K.",
	author = "Syoubu K.",
	author = "Fukui Y.",
	title = "On the speed-up of lock up time in the PLL frequency synthesizer",
	journal = "International Journal of Electronics",
	volume = "84",
	year = "1 February 1998",
	abstract = "A new speed-up method of lock up time is proposed for the phase locked loop (PLL) frequency synthesizer in the local oscillation circuit of a radio receiver. Doubling of reference frequency is achieved by using a new (N + 1/2) programmable divider which enables a half division ratio, compared with that of a conventional divider, and it leads to a bigger loop gain K and the speed-up of lock up time. The experimental results of lock up time will be given together with the spectrum of the output frequency.",
	pages = "123-130(8)",
	url = "http://www.ingentaconnect.com/content/tandf/tetn/1998/00000084/00000002/art00004"
}