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Publisher: Taylor and Francis Ltd

Volume 15, Number 3, 1 January 2002

Timing Analysis and Optimization for DSM IC--Guest Editorial
pp. 555-556(2)
Author: Chen, Chien-In Henry

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Timing Challenges for Very Deep Sub-Micron (VDSM) IC
pp. 557-562(6)
Authors: Lin, Ichiang; Chen, Chien-In Henry

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Energy Efficient Signaling in Deep-submicron Technology
pp. 563-586(24)
Authors: Ben Dhaou, Imed; Parhi, Keshab K.; Tenhunen, Hannu

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Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation
pp. 587-594(8)
Authors: Lee, Yu-Min; Chen, Charlie Chung-Ping; Chang, Yao-Wen; Wong, D.F.

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Performance Driven Global Routing Through Gradual Refinement
pp. 595-604(10)
Authors: Hu, Jiang; Sapatnekar, Sachin S.

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Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation
pp. 605-618(14)
Authors: Arunachalam, Ravishankar; Blanton, Ronald DeShawn; Pileggi, Lawrence T.

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Timing-Driven-Testable Convergent Tree Adders
pp. 637-645(9)
Authors: Huang, Johnnie A.; Chen, Chien-In Henry

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Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis
pp. 647-666(20)
Authors: Xiao, Tong; Marek-Sadowska, Malgorzata

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