A 1.8 V 4 k FeRAM Chip Using 0.2 u Process and Novel Design Techniques

Authors: Mocaluk G.; Kalkur T.S.

Source: Integrated Ferroelectrics, Volume 56, Number 1, Volume 56/2003 , pp. 1151-1160(10)

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Abstract:

Due to the increasing demand for high speed, low voltage or low power applications, non-volatile memory becomes even more important and more challenging as technology advances. With ferroelectric memories, which provides fast write and fast read with relatively low power, the challenge is to provide a ferroelectric random access memory (FeRAM) chip that operates at low voltages with the smallest geometry available in the technology. In this paper, we present a 1.8 V 4 k bit ferroelectric memory chip design, with emphasis on core/core control, bit:cell determination and key circuit design as well as simulation results based on a 0.2 u CMOS double level metal process and ferroelectric process parameter assumptions.

Document Type: Research article

Affiliations: 1: Microelectronics Research Laboratories, Department of Electrical and Computer Engineering, University of Colorado at Colorado Springs, Colorado Springs, CO 80933-7150

Publication date: 2003-01-01

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