Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs

Authors: Sansaloni, T.; Pérez-Pascual, A.; Torres, V.; Valls, J.

Source: The Journal of VLSI Signal Processing, Volume 47, Number 2, May 2007 , pp. 183-187(5)

Publisher: Springer

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Abstract:

A scheme for reducing the hardware resources to implement on LUT-based FPGA devices the twiddle factors required in Fast Fourier Transform (FFT) processors is presented. The proposed scheme reduces the number of embedded block RAM for large FFTs and the number of slices for FFT lengths higher than 128 points. Results are given for Xilinx devices, but they can be generalized for other advanced LUT-based devices like ALTERA Stratix.

Keywords: Fast Fourier Transform; digital circuits; digital communications

Document Type: Research article

DOI: http://dx.doi.org/10.1007/s11265-007-0055-8

Affiliations: 1: Email: tmsansal@eln.upv.es

Publication date: 2007-05-01