The Journal of VLSI Signal Processing

Interleaved Trellis Coded Modulation and Decoder Optimizations for 10 Gigabit Ethernet over Copper
pp. 211-221(11)
Authors: Gu, Yongru; Parhi, Keshab

VHDL Implementation of the Fast Wavelet Transform
pp. 223-239(17)
Authors: Salama, Paul; Rizkalla, Maher; Eckbauer, Michael

Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems
pp. 241-255(15)
Authors: Chien, Shao-Yi; Hsieh, Bing-Yu; Huang, Yu-Wen; Ma, Shyh-Yih; Chen, Liang-Gee

Reciprocal and Reciprocal Square Root Units with Operand Modification and Multiplication
pp. 257-272(16)
Authors: Wires, Kent; Schulte, Michael

A Novel FPGA Architecture of a 2-D Wavelet Transform
pp. 273-284(12)
Authors: Palero, Ricardo; Gironés, Rafael; Cortes, Angel

Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2^m) Generated by AOPs
pp. 285-296(12)
Authors: Imaña, J.L.; Sánchez, J.M.

Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results
pp. 297-320(24)
Authors: Huang, Yu-Wen; Chen, Ching-Yeh; Tsai, Chen-Han; Shen, Chun-Fu; Chen, Liang-Gee

A Survey on Lifting-based Discrete Wavelet Transform Architectures
pp. 321-339(19)
Authors: Acharya, Tinku; Chakrabarti, Chaitali