Processor Enhancements for Media Streaming Applications

Authors: Bilavarn, S.¹; Debes, E.²; Vandergheynst, P.³; Diguet, J.⁴

Source: The Journal of VLSI Signal Processing, Volume 41, Number 2, September 2005 , pp. 225-234(10)

Publisher: Springer

Abstract:

The development of more processing demanding applications on the Internet (video broadcasting) on one hand and the popularity of recent devices at the user level (digital cameras, wireless videophones, ...) on the other hand introduce challenges at several levels. Today, such devices present processing capabilities and bandwidth settings that are inefficient to manage scalable QoS requirements in a typical media delivery framework. In this paper, we present an impact study of such a scalable data representation optimized for QoS (Matching Pursuit 3D algorithms) on processor architectures to achieve the best performance and power efficiency. A review of state of the art techniques for processor architecture enhancement let us expect promising opportunities from the latest developments in the reconfigurable computing research field. We present here the first design steps of an efficient reconfigurable coprocessor especially designed to cope with future video delivery and multimedia processing requirements. Architecture perspectives are proposed with respect to low development cost constraints, backward compatibilty and easy coprocessor usage using an original strategy based on a hardware/software codesign methodology.

Keywords: video coding; matching pursuit; multimedia processing; reconfigurable coprocessor; software profiling; hardware design space exploration; codesign

Document Type: Research article

DOI: http://dx.doi.org/10.1007/s11265-005-6652-5

Affiliations: 1: Signal Processing Institute, Swiss Federal Institute of Technology (EPFL), Switzerland, Email: sebastien.bilavarn@epfl.ch 2: Architecture Research Lab, Intel, U.S.A., Email: eric.debes@intel.com 3: Signal Processing Institute, Swiss Federal Institute of Technology (EPFL), Switzerland, Email: pierre.vandergheynst@epfl.ch 4: Lab. of Electronics and REal Time Systems, LESTER, University of South Britanny, U.S.A., Email: jean-philippe.diguet@univ-ubs.fr

Publication date: 2005-09-01

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