Reviewing 4-to-2 Adders for Multi-Operand Addition

Author: Kornerup Peter

Source: The Journal of VLSI Signal Processing, Volume 40, Number 1, May 2005 , pp. 143-152(10)

Publisher: Springer

Buy & download fulltext article:

Price: $47.00 plus tax (Refund Policy)

Abstract:

Recently there has been quite a number of papers discussing the use of redundant 4-to-2 adders for the accumulation of partial products in multipliers, claiming one type to be superior to other types. This paper analyses a recent proposal of various 3- and 4-element redundant digit sets for radix 2, signed and unsigned, and compare their implementations using various encodings of the digits and carries. It is shown that theoretically they are equivalent, and differences in their implementations need only be very marginal. Another recent proposal for the use of the digit-set {0,1,2,3}, with a special 3-bit encoding of digits, is analyzed and some optimizations are shown, including the possibility of using a 2-bit encoding, with a quite significant saving in the wiring of a multiplier tree. All these proposed designs are shown to be equivalent to a standard 4-to-2, carry-save adder, except possibly for a few signal inversions.

Keywords: redundant adders; digit sets; digit encodings; multiplier trees

Document Type: Research article

DOI: http://dx.doi.org/10.1007/s11265-005-4943-5

Affiliations: 1: Department of Mathematics and Computer Science, University of Southern Denmark, Odense, Denmark, Email: kornerup@imada.sdu.dk

Publication date: 2005-05-01