The Journal of VLSI Signal Processing

Guest Editorial
pp. 5-5(1)
Authors: Ibrahim M.; Swartzlander E.

Further Reducing the Redundancy of a Notation Over a Minimally Redundant Digit Set
pp. 7-18(12)
Authors: Daumas M.; Matula D.W.

Fast CORDIC Algorithm Based on a New Recoding Scheme for Rotation Angles and Variable Scale Factors
pp. 19-29(11)
Authors: Chih J-C.; Chen S-G.

On-the-Fly Range Reduction
pp. 31-35(5)
Authors: Lefèvre V.; Muller J-M.

Error Analysis of the Kmetz/Maenner Algorithm
pp. 37-53(17)
Authors: Arnold M.; Bailey T.; Cowles J.

Multilevel Reverse-Carry Addition: Single and Dual Adders
pp. 55-74(20)
Authors: Bruguera J.D.; Lang T.

Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits
pp. 75-82(8)
Author: Moshnyaga V.G.

Energy Efficient Adiabatic Multiplier-Accumulator Design
pp. 83-103(21)
Authors: Suvakovic D.; Salama C.A.T.

Digit-Serial Complex-Number Multipliers on FPGAs
pp. 105-115(11)
Authors: Sansaloni T.; Valls J.; Parhi K.K.

A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling
pp. 117-124(8)
Authors: Chiang J-S.; Tsai M-S.

Implementation of the Exponential Function in a Floating-Point Unit
pp. 125-145(21)
Authors: Vázquez Á.; Antelo E.

An Efficient IDCT Processor Design for HDTV Applications
pp. 147-155(9)
Authors: Guo J-I.; Yen J-C.

An Integrated Systolic Array Design for Video Compression
pp. 157-169(13)
Authors: Tai P.L.; Liu C.T.; Wang J.S.

Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic
pp. 171-190(20)
Authors: Ramírez J.; García A.; Meyer-Bäse U.; Taylor F.; Lloris A.

A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems
pp. 191-197(7)
Authors: Wu X.; Chen H.; Sun Y.; Gai W.

An RNS Architecture for Quasi-Chaotic Oscillators
pp. 199-220(22)
Authors: Panella M.; Martinelli G.