The Flagged Prefix Adder and its Applications in Integer Arithmetic

Author: Burgess N.

Source: The Journal of VLSI Signal Processing, Volume 31, Number 3, July 2002 , pp. 263-271(9)

Publisher: Springer

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Abstract:

This paper shows how a parallel prefix adder computing S = A + B may be slightly modified to yield a new adder structure, called a “flagged prefix adder”, capable of returning the related computation pairs A + B and A + B + 1, or, if the bits of B are inverted, A - B and B - A. This adder is of use in digital communications applications and video compression, as well as arithmetic processor designs. The new adder uses 25% less transistors than the conditional-sum adder, which has been used previously in such situations.

Keywords: computer arithmetic; prefix adders; absolute difference; end-around carry

Language: English

Document Type: Regular paper

Affiliations: 1: Division of Electronics, School of Engineering, Cardiff University, Queen's Buildings, The Parade, Cardiff CF24 3TF, UK

Publication date: 2002-07-01