The Journal of VLSI Signal Processing

Digital Median Filters
pp. 191-206(16)
Authors: Breveglieri L.; Piuri V.

Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks
pp. 207-229(23)
Authors: Govindarajan R.; Gao G.R.; Desai P.

An Efficient VLSI Architecture for the Computation of 1-D Discrete Wavelet Transform
pp. 231-241(11)
Authors: Premkumar A.B.; Madhukumar A.S.

Synthesis and Optimization of Combinational Interface Circuits
pp. 243-261(19)
Authors: Chung K-S.; Gupta R.K.; Kim T.; Liu C.L.

The Flagged Prefix Adder and its Applications in Integer Arithmetic
pp. 263-271(9)
Author: Burgess N.