Low Power Encoding Techniques for Dynamically Reconfigurable Hardware

Authors: Kretzschmar C.¹; Siegmund R.²; Müller D.³

Source: The Journal of Supercomputing, Volume 26, Number 2, September 2003 , pp. 185-203(19)

Publisher: Springer

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Abstract:

In this paper, an approach to the implementation of digital systems is presented which utilizes dynamic hardware reconfiguration in order to automatically minimize the power dissipated on module interconnections such as system buses during system run time. Reduction of power dissipation is achieved by means of an activity-reducing system bus encoding technique. Encoder and decoder are implemented with dynamically reconfigured code tables which contain a transition minimizing code that is periodically recomputed during run time of the system in order to adapt to variations in the statistical parameters of the encoded data stream. We present the theoretical basics and an efficient implementation of a corresponding coder-decoder system. Experimental results showed a reduction in bus transition activity of up to 41%.

Keywords: low power; transition minimizing bus encoding; dynamic reconfiguration

Language: English

Document Type: Research article

Affiliations: 1: Department of Systems and Circuit Design, Chemnitz University of Technology, 09126 Chemnitz, Germany clkre@infotech.tu-chemnitz.de 2: Department of Systems and Circuit Design, Chemnitz University of Technology, 09126 Chemnitz, Germany rsie@infotech.tu-chemnitz.de 3: Department of Systems and Circuit Design, Chemnitz University of Technology, 09126 Chemnitz, Germany

Publication date: 2003-09-01