Thermally Oxidized InAlN of Different Compositions for InAlN/GaN Heterostructure Field-Effect Transistors

Authors: Kordoš, P.1; Mikulics, M.2; Stoklas, R.3; Čičo, K.3; Dadgar, A.4; Grűtzmacher, D.2; Krost, A.4

Source: Journal of Electronic Materials, Volume 41, Number 11, November 2012 , pp. 3013-3016(4)

Publisher: Springer

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Abstract:

Properties of InAlN/GaN heterostructure field-effect transistors with thermally oxidized (750°C, 2 min) InAlN barrier layers of different compositions (InN = 13%, 17%, and 21%) were evaluated. The saturation drain current was inversely proportional to the InN content and was lower than that obtained with nonoxidized devices. From the capacitance measurement, the resulting sheet charge density decreased from 1.1 × 1013 cm−2 to 0.6 × 1013 cm−2 with increased InN content, and it was only approximately 50% of that of the nonoxidized counterparts. The oxide thickness of approximately 1 nm was extracted from the zero-bias capacitances. The pulsed measurements yielded a very high gate lag independent from the InAlN composition (the pulsed-to-static drain current ratio was ∼0.5 for a 200-ns pulse width). On the other hand, a significantly lower gate lag was observed on nonoxidized SiN x passivated InAlN/GaN devices. The results demonstrate that a high density of trap states was created in the thermally oxidized InAlN/GaN structures.

Keywords: InAlN/GaN HFETs; thermal oxidation; trap states

Document Type: Research Article

DOI: http://dx.doi.org/10.1007/s11664-012-2096-4

Affiliations: 1: Department of Microelectronics, Slovak University of Technology, 81219, Bratislava, Slovakia, Email: peter.kordos@savba.sk 2: Research Centre Jülich, 52435, Jülich, Germany 3: Department of Microelectronics, Slovak University of Technology, 81219, Bratislava, Slovakia 4: Institute of Experimental Physics, University Magdeburg, 39016, Magdeburg, Germany

Publication date: November 1, 2012

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