CdZnTe graded buffer layers for HgCdTe/Si integration

Authors: Groenert, M.; Markunas, J.

Source: Journal of Electronic Materials, Volume 35, Number 6, June 2006 , pp. 1287-1292(6)

Publisher: Springer

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Abstract:

To investigate the potential benefits of compositional grading for dislocation control in CdTe/Si growth, Cd_1−xZn_xTe buffer layers with x graded smoothly from 1 to 0 have been deposited on Si (211) surfaces. Growth has been characterized using reflection high-energy electron diffraction (RHEED), x-ray diffraction (XRD), and etch pit density measurements. XRD showed an increase in rocking curve full-width at half-maximum (FWHM) and global lattice tilt with decreasing x values. Tilt was also observed to increase as buffer growth temperature was increased. Final surface dislocation densities did not decrease below 7×10⁶ cm⁻². EPD surface dislocation measurements showed reduced dislocation densities and dislocation clustering along the <EquationSource Format="TEX"><![CDATA[ $$[1bar 10]$$ ]]></EquationSource> and <EquationSource Format="TEX"><![CDATA[ $$[bar 110]$$ ]]></EquationSource> lines for CdTe cap layers grown on partially graded Cd_1−xZn_xTe buffer layers with slow compositional grading rates. Samples grown with faster grading rates showed higher final EPD values, with dislocations clustering along the <EquationSource Format="TEX"><![CDATA[ $$[31bar 2]$$ ]]></EquationSource> and <EquationSource Format="TEX"><![CDATA[ $$[bar 1bar 32]$$ ]]></EquationSource> lines.

Keywords: CdZnTe; CdTe/Si; dislocations; tilt; graded buffer Z

Document Type: Research article

DOI: http://dx.doi.org/10.1007/s11664-006-0256-0

Affiliations: 1: Email: michael.groenert@nvl.army.mil

Publication date: 2006-06-01