Hybrid Cache Analysis in Running Time Verification of Embedded Software

Authors: Wolf F.1; Staschulat J.2; Ernst R.3

Source: Design Automation for Embedded Systems, Volume 7, Number 3, October 2002 , pp. 271-295(25)

Publisher: Springer

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Abstract:

Verification of software running time is essential in embedded system design with real-time constraints. Simulation with incomplete test patterns is unsafe for complex architectures when software running times are input data dependent. Formal analysis of such dependencies leads to software running time intervals rather than single values. These intervals depend on program properties, execution paths and states of processes, as well as on the target architecture. In the target architecture, caches have a major influence on software running time. Current cache analysis techniques as a part of running time analysis approaches combine basic block level cache modeling with explicit or implicit program path analysis. We present an approach that extends instruction and data cache modeling from basic blocks to program segments thereby increasing the overall running time analysis precision. We combine it with data flow analysis based prediction of cache line contents. This novel cache analysis approach shows high precision in the presented experiments.

Keywords: Cache analysis; timing analysis; worst-case execution-time

Language: English

Document Type: Research article

Affiliations: 1: Institut für Datentechnik and Kommunikationsnetze, TU Braunschweig Hans-Sommer-Str. 66, D-38106 Braunschweig, Germany E-mail: wolf@ida.ing.tu-bs.de 2: Institut für Datentechnik and Kommunikationsnetze, TU Braunschweig Hans-Sommer-Str. 66, D-38106 Braunschweig, Germany E-mail: staschulatOida.ing.tu-bs.de 3: Institut für Datentechnik and Kommunikationsnetze, TU Braunschweig Hans-Sommer-Str. 66, D-38106 Braunschweig, Germany E-mail: ernst@ida.ing.tu-bs.de

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