A Low Voltage 14-Bit Self-Calibrated CMOS DAC with Enhanced Dynamic Linearity

Authors: Saeedi, S.¹; Mehrmanesh, S.²; Atarodi, M.³

Source: Analog Integrated Circuits and Signal Processing, Volume 43, Number 2, May 2005 , pp. 137-145(9)

Publisher: Springer

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Abstract:

A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. To improve dynamic linearity at high frequencies, a track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are less than 0.35 and 0.25 LSB, respectively. The DAC is functional up to 400MS/s with SFDR better than 71 dB in the Nyquist band. The circuit has been designed and simulated in a standard 0.18 u CMOS technology.

Keywords: digital to analog converter (DAC); self calibration; dynamic nonlinearities; track/attenuate output stage

Document Type: Research article

DOI: http://dx.doi.org/10.1007/s10470-005-6787-0

Affiliations: 1: Sharif University of Technology, Iran, Email: saeedi@mehr.sharif.edu 2: Iran Microelectronics Research Center, Iran, 3: Mixcore Design, Canada,

Publication date: 2005-05-01