Single-Chip Stereo Imager: ISCAS 2002 Special Issue on Smart Sensors (Guest Editors: Orly Yadid-Pecht and Ralph Etienne-Cummings)
Authors: Philipp R.M.1; Etienne-Cummings R.2
Source: Analog Integrated Circuits and Signal Processing, Volume 39, Number 3, June 2004 , pp. 237-250(14)
Publisher: Springer
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Abstract:
This paper presents a complete Single-chip Stereo Imager (SSI), incorporating two 128 × 128 pixel current-mode imagers and current-mode analog computation circuitry on a single integrated circuit. A modified version of block matching is used to find the stereo disparity at each location in the field of view. At each location, the sum-of-absolute-difference is computed, in parallel, for each possible disparity. The SSI is capable of operation at 66.1 million checked disparities per second (41 fps) while drawing 15.2 mA from a 5 V supply, including imagers and computation circuits. The SSI occupies 4.23 × 4.23 mm2 of area in a 0.5
m (
= 0.35 m) 5 V, 3-metal, 2-poly CMOS process.
Keywords: stereo vision; current-mode imager; vision; focal-plane processing; analog image processing
Document Type: Research article
DOI: 10.1023/B:ALOG.0000029660.01471.13
Affiliations: 1: Department of Electrical & Computer Engineering, Johns Hopkins University, Baltimore, MD, USA., Email: rphilipp@jhu.edu 2: Department of Electrical & Computer Engineering, Johns Hopkins University, Baltimore, MD, USA
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