Minimizing Phase Noise Variation in CMOS Ring Oscillators
Authors: Srinivasan V.1; Islam S.K.2; Blalock B.J.2
Source: Analog Integrated Circuits and Signal Processing, Volume 34, Number 3, March 2003 , pp. 259-263(5)
Publisher: Springer
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Abstract:
The variation of phase noise across the frequency of operation of a CMOS ring oscillator is described analytically. The delay element of the ring oscillator considered comprises of a source-coupled differential pair with an active load element. In this circuit topology where the frequency of oscillation is varied by changing the resistance of the load, theory derived in this work predicts that phase noise will remain constant if constant output swing is maintained. Such an oscillator is designed in a 0.5 
m CMOS process and the simulation results verify the theoretical analysis. Consequently, an oscillator design methodology is provided that dramatically reduces the phase noise optimization problem to just one frequency within the oscillator's output frequency range.
Keywords: phase noise; timing jitter; ring oscillator
Language: English
Document Type: Research article
Affiliations: 1: School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332 gtg652j@mail.gatech.edu 2: Department of Electrical and Computer Engineering, University of Tennessee, Knoxville, TN 37996
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