A Symbolic Pole/Zero Extraction Methodology Based on Analysis of Circuit Time-Constants
Authors: Guerra O.1; Rodríguez-García J.D.2; Fernández F.V.3; Rodríguez-Vázquez A.3
Source: Analog Integrated Circuits and Signal Processing, Volume 31, Number 2, May 2002 , pp. 101-118(18)
Publisher: Springer
- Free Content
- New Content
- Subscribed Content
- Free Trial Content
Abstract:
This paper introduces a methodology for symbolic pole/zero extraction based on the formulation of the time-constant matrix of the circuits. This methodology incorporates approximation techniques specifically devoted to achieve an optimum trade-off between accuracy and complexity of the symbolic root expressions. The capability to efficiently handle even large circuits will be demonstrated through several practical circuits.
Keywords: analog circuits; symbolic analysis; pole/zero analysis; simplification techniques
Language: English
Document Type: Regular paper
Affiliations: 1: Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, Edificio CNM, Avda. Reina Mercedes s/n., E-41012-Sevilla, Spain Tel.: 34 955056666, Fax: 34 955056686 pacov@imse.cnm.es 2: Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, Edificio CNM, Avda. Reina Mercedes s/n., E-41012-Sevilla, Spain Tel.: 34 955056666, Fax: 34 955056686 pacov@imse.cnm.es 3: Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, Edificio CNM, Avda. Reina Mercedes s/n., E-41012-Sevilla, Spain Tel.: 34 955056666, Fax: 34 955056686 and Área de Electrónica, Escuela Superior de Ingenieros, Edificio Plaza de América, Isla de la Cartuja s/n., E-41092-Sevilla, Spain Tel.: 34 954487378, Fax: 34 954487379 pacov@imse.cnm.es
- Free Content
- New Content
- Subscribed Content
- Free Trial Content
Click here for Page Help