A CMOS Monolithic Image-Reject Filter

Authors: Chang Y.¹; Choma Jr. J.²; Wills J.³

Source: Analog Integrated Circuits and Signal Processing, Volume 28, Number 1, July 2001 , pp. 43-52(10)

Publisher: Springer

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Abstract:

A CMOS inductorless image-reject filter based on active RLC circuitry is discussed and designed with the emphasis on low-noise, low-power, and gigahertz-range circuits. Two Q-enhancement techniques are utilized to circumvent the low Q characteristics inherent in the simple feedback circuit. The frequency tuning is almost independent of Q tuning, facilitating the design of the automatic tuning circuitry. The stability and the tuning scheme of the filter are also discussed. Simulations using 0.6 m CMOS technology demonstrate the feasibility of the tunable image-reject filter for GSM wireless applications. Simulation results show 4.75 dB voltage gain, 9.5 dB noise figure, and -20 dBm IIP3 at a passband centered at 947 MHz. The image signal suppression is 60 dB at 1089 MHz and the power consumption is 27 mW.

Keywords: RF filter; notch filter; CMOS continuous-time filter

Language: English

Document Type: Regular paper

Affiliations: 1: Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90089 yuyuchan@usc.edu 2: Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90089 johnc@usc.edu 3: Information Sciences Institute, University of Southern California, Marina del Rey, CA 90292 jackw@isi.edu

Publication date: 2001-07-01