Electrical characterization of high-dielectric-constant/SiO2 metal–oxide–semiconductor gate stacks by a conductive atomic force microscope
Authors: Blasco, X.; Porti, M.; Nafría, M.; Aymerich, X.; Pétry, J.; Vandervorst, W.
Source: Nanotechnology, Volume 16, Number 9, September 2005 , pp. 1506-1511(6)
Publisher: Institute of Physics Publishing
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Abstract:
A conductive atomic force microscope (CAFM) has been used to study, at the nanometre scale, the dependence of the electrical behaviour on the post-deposition annealing temperature (TA) and the dielectric reliability of ultrathin high-dielectric-constant/SiO2 MOS gate stacks. It has been observed that for high enough TA the conduction becomes more inhomogeneous, leading to the formation of leaky spots that could be a problem for the integration of these layers in a standard CMOS microelectronic process. The CAFM has also revealed that the values of some parameters related to the dielectric reliability, such as the area of the breakdown spot (i.e. a region that has lost its insulating properties owing to electrical stress), are of the same order for SiO2 layers and high-dielectric-constant/SiO2 stacks. Moreover, different conduction regimes, which cannot be detected by standard electrical characterization techniques, have been observed.Document Type: Research article
DOI: 10.1088/0957-4484/16/9/016
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