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FPGA-Based Interpolation for Motor Encoders

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Abstract:

This paper presents the design and implementation of a novel but simple interpolation algorithm implemented in a field programmable gate array (FPGA) to raise the resolution of incremental encoders. The incremental encoder is the most popular sensor on servo control systems by considering the factors of performance and cost. The higher resolution the encoder, the wider range the motor can rotate smoothly and accurately. A frequency-independent phase shift (FIPS) circuit is employed to delay square-waveform signals of channels A and B of the encoder by some specified electric angles. These delayed and paired signals are performed by simple exclusive-or function to generate new squared signals of channels A and B with two-power order frequency of original channel A. Compared with conventional methods, this algorithm provides many merits, such as square waveforms required, independence of operating frequency, applicable to any motor speeds, without need of any analog-to-digital converters (ADCs), resistors, or operational amplifiers. The simulation results of interpolating by four times by using VHDL (very high speed integrated circuit hardware description language) are first shown. The effectiveness of the proposed algorithm will be demonstrated through the experimental results of open-loop function test and closed-loop speed responses.

Keywords: FPGA; INCREMENTAL ENCODERS; INTERPOLATION

Document Type: Research Article

DOI: http://dx.doi.org/10.1166/sl.2012.2274

Publication date: May 1, 2012

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