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Simulation, Fabrication and Characterization of Sol–Gel Deposited ZnO Based Thin Film Transistors

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A bottom-gate thin film transistor (TFT) with ZnO as the channel layer and SiO2 as insulating layer has been fabricated and characterized. Simulation of this TFT is also carried out by using the commercial software modeling tool ATLAS™ from Silvaco-International. The simulated global characteristics of the device were compared and contrasted with those measured experimentally. The experimental results are in fairly good agreement with those obtained from simulation. The TFT exhibited an off-current of 2.5 × 10–7 A. The values of field effect channel mobility and on/off current ratio extracted for the device, measured 11 cm 2/V · s and ∼ 102 respectively. The value of threshold voltage was found to be 1.3 V.
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Document Type: Research Article

Publication date: 2012-02-01

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  • Science of Advanced Materials (SAM) is an interdisciplinary peer-reviewed journal consolidating research activities in all aspects of advanced materials in the fields of science, engineering and medicine into a single and unique reference source. SAM provides the means for materials scientists, chemists, physicists, biologists, engineers, ceramicists, metallurgists, theoreticians and technocrats to publish original research articles as reviews with author's photo and short biography, full research articles and communications of important new scientific and technological findings, encompassing the fundamental and applied research in all latest aspects of advanced materials.
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