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Towards Highly Linear High Resolution Successive Approximation Register ADCs for the Internet of Things

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This paper presents an effective technique to improve both the static and dynamic linearity simultaneously without sacrificing the sampling rate in high-resolution successive approximation register (SAR) analog-to-digital converter (ADC) for Internet-of-Things (IoT) application. Results show that the technique proposed can improve the root-mean-square (rms) of differential non-linearity (DNL) from 1.96 LSB to 0.52 LSB and rms of integral non-linearity (INL) from 3.24 LSB to 0.55 LSB; On the other hand, the averaged Signal-to-Noise-and-Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) of 13.4 dB and near 20 dB are improved respectively, which makes it suitable for accurate and linear smart sensor nodes in IoT sensing systems.
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Keywords: ANALOG-TO-DIGITAL CONVERTER (ADC); CAPACITOR MISMATCH; DIFFERENTIAL NONLINEARITY (DNL); INTEGRAL NONLINEARITY (INL); SUCCESSIVE APPROXIMATION REGISTER (SAR)

Document Type: Short Communication

Publication date: 01 December 2017

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  • Nanoscience and Nanotechnology Letters (NNL) is a multidisciplinary peer-reviewed journal consolidating nanoscale research activities in all disciplines of science, engineering and medicine into a single and unique reference source. NNL provides the means for scientists, engineers, medical experts and technocrats to publish original short research articles as communications/letters of important new scientific and technological findings, encompassing the fundamental and applied research in all disciplines of the physical sciences, engineering and medicine.
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