Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating

Authors: Sathanur, A.; Benini, L.; Macii, A.; Macii, E.; Poncino, M.

Source: Journal of Low Power Electronics, Volume 5, Number 1, April 2009 , pp. 113-121(9)

Publisher: American Scientific Publishers

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Abstract:

The use of sleep transistors as power-gating devices to cut-off sub-threshold leakage stand-by currents has become a very popular solution to tackle the rise of leakage consumption in nanometer CMOS circuits. Clustered power-gating is now the de-fact standard for application of this leakage saving technique in industry. Cell clustering, sleep transistor sizing and peak current estimation are among the key steps of state-of-the-art clustered power-gating methodologies. In this work, we propose to exploit the information on the temporal variations of the discharge currents of the gates in a circuit to improve the quality of the solutions generated by an existing cell clustering algorithm. This translates to power-gated circuits with lower leakage consumption compared to implementations based clusters formed assuming a time-invariant, worst-case behavior of the currents drawn by the cells. The achieved leakage savings can be as high as 17%.

Keywords: LEAKAGE POWER OPTIMIZATION; POWER-GATING; SLEEP TRANSISTOR INSERTION

Document Type: Research article

DOI: http://dx.doi.org/10.1166/jolpe.2009.1004

Publication date: 2009-04-01

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The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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