Authors: Devanathan, V.R.; Ravikumar, C.P.; Mehrotra, Rajat; Kamakoti, V.

Source: Journal of Low Power Electronics, Volume 4, Number 1, April 2008 , pp. 101-110(10)

Publisher: American Scientific Publishers

Abstract:

In sub-70 nm technologies, leakage power becomes a significant component of the total power. Designers address this concern by extensive use of adaptive voltage scaling techniques to reduce dynamic as well as leakage power. Low-power scan test schemes that have evolved in the past primarily address dynamic power reduction, and are less effective in reducing the total power. This paper proposes a Power-Managed Scan (PMScan) scheme which exploits the presence of adaptive voltage scaling logic to reduce test power. Some practical implementation challenges that arise when the proposed scheme is employed on industrial designs are also discussed. Experimental results on benchmark circuits and industrial designs show that employing the proposed technique leads to a significant reduction in dynamic and leakage power. The proposed method can also be used as a vehicle to trade-off test application time with test power by suitably adjusting the scan shift frequency and scan-mode power supplies.

Keywords: TEST POWER; LEAKAGE POWER; POWER MANAGEMENT; VOLTAGE SCALING; TEST TIME

Document Type: Research article

DOI: http://dx.doi.org/10.1166/jolpe.2008.150

Publication date: 2008-04-01

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• The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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