Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits

Authors: Tajalli, Armin; Muller, Paul; Leblebici, Yusuf

Source: Journal of Low Power Electronics, Volume 3, Number 3, December 2007 , pp. 345-354(10)

Publisher: American Scientific Publishers

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Abstract:

This article describes some techniques for implementing low-power clock and data recovery (CDR) circuits based on gated-oscillator (GO) topology for short distance applications. Here, the main tradeoffs in design of a high performance and power-efficient GO CDR are studied and based on that a top-down design methodology is introduced such that the jitter tolerance (JTOL) and frequency tolerance (FTOL) requirements of the system are simultaneously satisfied. A test chip has been implemented in standard digital 0.18 μm CMOS while the proposed CDR circuit consumes only 10.5 mW and occupies 0.045 mm² silicon area in 2.5 Gbps data bit rate. Measurement results show a good agreement to analyses proofs the capabilities of the proposed approach for implementing low-power GOCDRs.

Keywords: CMOS ANALOG INTEGRATED CIRCUITS; CLOCK AND DATA RECOVERY CIRCUIT; GATED-OSCILLATOR CDR; POWER-AWARE DESIGN; CHIP-TO-CHIP INTERCONNECTION

Document Type: Research article

DOI: http://dx.doi.org/10.1166/jolpe.2007.145

Publication date: 2007-12-01

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The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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