Low-Power Hierarchical Scan Test for Multiple Clock Domains

Authors: Arasu, T. Senthil; Ravikumar, C.P.; Nandy, S.K.

Source: Journal of Low Power Electronics, Volume 3, Number 1, April 2007 , pp. 106-118(13)

Publisher: American Scientific Publishers

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Abstract:

System-on-chip designs include intellectual property cores such as microprocessors, microcontrollers, digital signal processors, I/O interfaces, and hardware accelerators which correspond to different clock domains. Scan-based testing of multiple clock domain circuits poses several challenges. In this paper, we discuss these challenges with the intent of reducing test application time and test power. A hierarchical scan test technique called "divide-and-conquer" (DNC) scan is often used in the industry to address the issues of test generation complexity and test power. We improve this technique by using a clock-domain based partitioning called "Virtual Divide-and-Conquer" (VDNC) so as to eliminate several shortcomings of DNC scan and reduce test application time and test power. We provide the results of VDNC scan on an industrial-strength ASIC and show that it outperforms the conventional schemes without losing the benefits of hierarchical scan.

Keywords: DESIGN-FOR-TEST; SCAN TEST ARCHITECTURE; HIERARCHICAL SCAN TEST; MULTI-CLOCK DOMAIN ASICS

Document Type: Research article

DOI: http://dx.doi.org/10.1166/jolpe.2007.117

Publication date: 2007-04-01

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The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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