Exploiting Speculation Cost Prediction in Power-Aware Applications

Authors: Atoofian, Ehsan; Baniasadi, Amirali; Aasaraai, Kaveh

Source: Journal of Low Power Electronics, Volume 3, Number 1, April 2007 , pp. 43-53(11)

Publisher: American Scientific Publishers

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Abstract:

Branch prediction is essential in modern high-performance processors. Unfortunately, mispredictions are inevitable and cost energy. We study branch mispredictions and show that there are a few high-cost mispredictions that account for most of the cost. We show that a low-cost branch instruction tends to remain low-cost in future reappearances. We exploit this predictability and introduce a simple yet efficient cost predictor that identifies low-cost branch instructions with an accuracy above 93%. We use our findings and introduce two cost-aware power optimizations. First we introduce cost-aware branch prediction. In cost-aware branch prediction we exploit a simple low-power predictor for low-cost branch instructions and leave the more complex and energy hungry predictor for branch instructions with higher costs. On average, we reduce branch predictor access frequency up to 59%with a maximum performance loss of 0.23%. This results in up to 14%branch predictor energy reduction. Second we introduce cost-aware checkpointing. In cost-aware checkpointing, we use an aggressive and fast recovery mechanism only for high-cost branches. For low-cost branches we use a slower but more power efficient mechanism. On average, we reduce RAT access frequency (up to 69%) and power dissipation (up to 25.1%) for processors with different number of recovery buffer entries. By using recovery resources more efficiently we also improve overall processor performance (up to 20%).

Keywords: BRANCH PREDICTION; COST PREDICTABILITY; CHECKPOINTING; POWER-AWARE DESIGN

Document Type: Research article

DOI: 10.1166/jolpe.2007.110

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