IngentaConnect A Low Power, Scalable and Runtime Customizable Microprocessor Arc...

Authors: Notarangelo, Giuseppe; Pappalardo, Francesco; Salurso, Elena; Guidetti, Elio

Source: Journal of Low Power Electronics, Volume 3, Number 1, April 2007 , pp. 36-42(7)

Publisher: American Scientific Publishers

Abstract:

A very important rule into communication is played by images. As consequence the commercial value of portable devices has been growth if they integrate electronic sensors for image acquisition and the availability of user-friendly image-editing software. The speed in extracting and processing information coupled to the ability to enhance the quality of a digital image with easy procedures, represents the challenge of combining hardware (microprocessors) and software (algorithms) partitioning in VLSI design for image processing. Moreover, the low-power design methodology and the area size are the right supervisor guides to maintain acceptable the time-to-use of the modern image processing devices and their own portability. In this context, this paper exposes an easily scalable and runtime customizable microprocessor architecture with a structure that combines the paradigm of vectorial processing and Very Long Instruction Word (VLIW) with high utilization of parallel resources on both data and instruction level. The microprocessor has shown no significant area increase, compared with the ST200 VLIW architecture which is based onto, while its performance is improved by 2.4 up to 4 times. Moreover the solution proposed implies significant power savings (about 32.4%) due to an instruction level power control mechanism, to the drastic reduction of code size and a massive use of well known low power techniques. For this reason it represents a possible answer for low energy dissipation, executing image processing applications.

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A Low Power, Scalable and Runtime Customizable Microprocessor Architecture for Image Processing