IngentaConnect Estimation of Leakage Power Consumption and Parametric Yield Base...

Authors: Wang, Wei-Shen; Orshansky, Michael

Source: Journal of Low Power Electronics, Volume 3, Number 1, April 2007 , pp. 1-12(12)

Publisher: American Scientific Publishers

Abstract:

The increasing variability of process and environmental parameters has a significant impact on the leakage power dissipation and parametric yield of chip designs. In practice, estimation of the leakage dissipation and parametric yield, however, becomes extremely difficult due to the limited availability of parameter characterization during the early design phase. Existing statistical leakage estimation approaches heavily rely on the idealized distributional properties of parameter, lacking the capabilities of handling realistic distributions of parameters. On the other hand, estimation approaches based on intervals of parameters often lead to over-pessimistic power estimates, thus resulting in the over-conservatism. This paper proposes a robust estimation strategy for the chip-level leakage dissipation and parametric yield. Based on the rigorous notions of non-parametric robust statistics, the proposed strategy permits reliable leakage estimation using incomplete probabilistic descriptions of parameters: the intervals and the limited number of moments (e.g., mean and variance). Full or partial probabilistic descriptions of parameters can be described by robust representations, and used to estimate the guaranteed bounds for the chip leakage distribution and parametric yield. Compared to the traditional interval-based estimation strategy, the proposed robust estimation algorithm can reduce the over-conservatism of the leakage estimates. Experimental results show that the conservatism is reduced by 5-13% for the total leakage dissipation at the 99th percentile across all frequency bins.

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Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters