Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power Applications

Authors: Navarro-Botello, Victor; Montiel-Nelson, Juan A.; Nooshabadi, Saeid

Source: Journal of Low Power Electronics, Volume 2, Number 2, August 2006 , pp. 300-307(8)

Publisher: American Scientific Publishers

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Abstract:

This paper presents the design of low power high performance arithmetic circuits using the feedthrough logic (FTL) concept. FTL is ideally suited for the circuit design where the critical path is made of a large cascade of inverting gates. Its high fanout and high switching frequencies are due to both lower delay and dynamic power consumption. Low power FTL arithmetic circuits provides for smaller propagation delay time (2.6 times), lower energy consumption (31%), and similar combined delay, power consumption, and active area product, when compared with the standard CMOS technologies.

Keywords: FEEDTHROUGH LOGIC; LOW POWER ARITHMETIC CIRCUITS; HIGH SPEED CMOS TECHNIQUES

Document Type: Conference report

DOI: http://dx.doi.org/10.1166/jolpe.2006.066

Publication date: 2006-08-01

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The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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