Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, and Threshold Voltage Selection

Authors: Bhardwaj, Sarvesh; Cao, Yu; Vrudhula, Sarma

Source: Journal of Low Power Electronics, Volume 2, Number 2, August 2006 , pp. 240-250(11)

Publisher: American Scientific Publishers

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Abstract:

This paper proposes a novel methodology for statistical leakage minimization of digital circuits. A function of mean and variance of the circuit leakage is minimized with constraint on α-percentile of the path delays using physical delay models fitted to a 90-nm industrial technology. Since the leakage is a strong function of the threshold voltage and gate length, considering them as design variables can provide significant amount of power savings. The formulated leakage minimization problem is shown to be a multivariable convex optimization problem under specific variable transformations. We demonstrate that our statistical optimization can lead to more than 50% reduction in the 90-percentile leakage for a 6% increase in the required time constraint.

Keywords: LEAKAGE MINIMIZATION; STATISTICAL OPTIMIZATION; GATE SIZING; CONVEX OPTIMIZATION; PROBABILITY; GATE LENGTH BIASING

Document Type: Research article

DOI: http://dx.doi.org/10.1166/jolpe.2006.065

Publication date: 2006-08-01

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The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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