IngentaConnect Gate Sizing and Vt Assignment for Active-Mode Leakage Power Reduc...

Authors: Gao, Feng; Hayes, John P.

Source: Journal of Low Power Electronics, Volume 2, Number 2, August 2006 , pp. 230-239(10)

Publisher: American Scientific Publishers

Abstract:

Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduce leakage power. Assuming a standard-cell-based design flow where the available cell sizes and threshold voltages V_t's) are given, we model the optimization as a mixed-integer linear programming (MILP) problem. In addition to the exact model, two faster approximate MILP models are proposed, along with CAD tools that generate the models automatically. We present experimental results which show that optimal designs derived from the exact MILP model can achieve the same performance as all-low-V_t unit-size designs, but with only one third the leakage power. In fact, the leakage power consumption of the optimal designs is shown to be only slightly higher than that of the corresponding all-high-V_t ones. The approximate MILP models can be solved about 25 times faster than the optimal model with negligible errors. We also show that the exact and approximate MILP models greatly outperform a TILOS-like sensitivity-based approach, a typical heuristic approach. All the proposed models can be extended to take dynamic power and multiple supply voltages into consideration.

Keywords: DUAL VT; GATE SIZING; LEAKAGE; MIXED-INTEGER LINEAR PROGRAMMING; POWER OPTIMIZATION

Document Type: Research article

DOI: 10.1166/jolpe.2006.056

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Gate Sizing and Vt Assignment for Active-Mode Leakage Power Reduction

Gate Sizing and V_t Assignment for Active-Mode Leakage Power Reduction