Authors: Kulkarni, Sarvesh H.; Sylvester, Dennis

Source: Journal of Low Power Electronics, Volume 2, Number 2, August 2006 , pp. 217-229(13)

Publisher: American Scientific Publishers

Abstract:

Extensive research has proposed the use of multiple on-die power supplies (VDD) for reducing power consumption in CMOS circuits. In this work, we present design techniques and a detailed feasibility study for power delivery systems in dual VDD circuits. We first show that the total current to be delivered by the voltage supplies is significantly reduced in dual VDD circuits (by 20%-51% in studied benchmarks). This current reduction prompts various design strategies that can be employed to design the power delivery system. We describe issues that arise at the board and package levels and present a high-level model for the same. We then provide a new placement aware approach for designing on-die dual VDD power grids. Compared to existing methods, the dual VDD grids generated by our approach reduce the worst case and average voltage drop by up to 12.3% and 6.8%, respectively with no area overhead and frequently improving wire congestion. We also show that dual VDD circuits can afford lower on-die decoupling capacitance budgets.

Keywords: POWER DELIVERY; LOW-POWER DESIGN; MULTI-VDD DESIGN

Document Type: Research article

DOI: http://dx.doi.org/10.1166/jolpe.2006.068

Publication date: 2006-08-01

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• The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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