Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design

Authors: Di, Jia; Yuan, J.S.

Source: Journal of Low Power Electronics, Volume 2, Number 2, August 2006 , pp. 201-216(16)

Publisher: American Scientific Publishers

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Abstract:

Energy-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Because of the encoding format and operating sequence, dual-rail encoding circuits do not naturally energy aware to the changing of input precisions. A novel technique named Zero Insertion for designing energy-aware arithmetic circuits in dual-rail encoding logic is developed. By using Null to replace the redundant Data 0's in high order bits, the designed circuits have significant energy savings as well as latency reduction at different input precisions while maintaining speed-independency. Parallel adders, multipliers, and a rank-order filter, have been designed and simulated to demonstrate the effectiveness of this technique. The overhead and additional costs in the control circuit are also discussed.

Keywords: ENERGY-AWARENESS; DUAL-RAIL ENCODING; NCL; ZERO INSERTION; BIT-WISE COMPLETION

Document Type: Research article

DOI: 10.1166/jolpe.2006.063

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