Communication Power Optimization for Network-on-Chip Architectures

Authors: Shin, Dongkun; Kim, Jihong

Source: Journal of Low Power Electronics, Volume 2, Number 2, August 2006 , pp. 165-176(12)

Publisher: American Scientific Publishers

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Abstract:

Network-on-Chip (NoC) architecture is emerging as a practical interconnection architecture for future systems-on-chip products. In this paper, an energy-efficient static algorithm which optimizes the energy consumption of task communications in NoCs with voltage scalable links is proposed. In order to find optimal link speeds, the proposed algorithm (based on a genetic formulation) globally explores the design space of NoC-based systems, including network topology, task assignment, tile mapping, routing path allocation, task scheduling, and link speed assignment. The experimental results demonstrate that the proposed design technique can reduce energy consumption by an average of 28% over existing techniques.

Keywords: NETWORK-ON-CHIP; DYNAMIC VOLTAGE SCALING; REAL-TIME SYSTEMS; LOW-POWER DESIGN

Document Type: Research article

DOI: http://dx.doi.org/10.1166/jolpe.2006.069

Publication date: 2006-08-01

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The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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