Communication Power Optimization for Network-on-Chip Architectures

Authors: Shin, Dongkun; Kim, Jihong

Source: Journal of Low Power Electronics, Volume 2, Number 2, August 2006 , pp. 165-176(12)

Publisher: American Scientific Publishers

Key:

- Free Content

- New Content

- Subscribed Content

- Free Trial Content

Abstract:

Network-on-Chip (NoC) architecture is emerging as a practical interconnection architecture for future systems-on-chip products. In this paper, an energy-efficient static algorithm which optimizes the energy consumption of task communications in NoCs with voltage scalable links is proposed. In order to find optimal link speeds, the proposed algorithm (based on a genetic formulation) globally explores the design space of NoC-based systems, including network topology, task assignment, tile mapping, routing path allocation, task scheduling, and link speed assignment. The experimental results demonstrate that the proposed design technique can reduce energy consumption by an average of 28% over existing techniques.

Keywords: NETWORK-ON-CHIP; DYNAMIC VOLTAGE SCALING; REAL-TIME SYSTEMS; LOW-POWER DESIGN

Document Type: Research article

DOI: 10.1166/jolpe.2006.069

The full text electronic article is available for purchase. You will be able to download the full text electronic article after payment.

$210.00 plus tax