Authors: Allu, Bramha; Zhang, Wei

Source: Journal of Low Power Electronics, Volume 2, Number 2, August 2006 , pp. 140-147(8)

Publisher: American Scientific Publishers

Abstract:

Power consumption has become a first order design consideration for both the high-performance microprocessors and embedded systems. Translation Look-aside Buffer (TLB), which is a small Content Addressable Memory (CAM) structure to assist in mapping virtual addresses to physical addresses, can consume a notable fraction of on-chip power (e.g., 17% on StrongARM SA110) and also has high power density. This paper proposes a novel compiler-directed approach to direct the instruction TLB (iTLB) energy conservation for VLIW processors without compromising performance. The idea is to resize the iTLB dynamically to fit the demands of applications at runtime based on the compiler's analysis. Since only a small portion of iTLB entries are actively accessed during the execution of loops, which typically take long execution time, we propose to resize the iTLB at the loop granularity. Our experiments show that such a strategy can effectively reduce the iTLB energy consumption by 81.3% on average with minimum impact on performance and hardware cost.

Keywords: INSTRUCTION TLB; ENERGY CONSUMPTION; COMPILER; DYNAMIC RESIZE

Document Type: Research article

DOI: http://dx.doi.org/10.1166/jolpe.2006.061

Publication date: 2006-08-01

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• The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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