Power – Performance Optimization for Custom Digital Circuits
Authors: Zlatanovici, Radu; Nikolić, Borivoje
Source: Journal of Low Power Electronics, Volume 2, Number 1, April 2006 , pp. 113-120(8)
Publisher: American Scientific Publishers
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Abstract:
This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to maximize the performance of digital circuits within a limited power budget by tuning various variables such as gate sizes, supply, and threshold voltages. It can employ different models to characterize the components. Analytical models usually lead to convex optimization problems where the optimality of the results is guaranteed. Tabulated models or an arbitrary timing signoff tool can be used if better accuracy is desired and although the optimality of the results cannot be guaranteed, it can be verified against a near-optimality boundary. The optimization examples are presented on 64-bit carry-lookahead adders. By achieving the power optimality of the underlying circuit fabric, this framework can be used by logic designers and system architects to make optimal decisions at the microarchitecture level.Keywords: POWER - PERFORMANCE OPTIMIZATION; CONVEX OPTIMIZATION; CMOS; STATIC TIMING; TIMING MODELS
Document Type: Research article
DOI: 10.1166/jolpe.2006.013
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