Abstract:

In Deep Sub-Micron technologies post-layout timing analysis has become the most critical phase in the verification of large System-on-Chip (SoC) designs with several power-hungry blocks. The impact of coupling capacitances has been adequately analyzed, and modern signal integrity analysis tools can effectively consider the crosstalk-induced delay. However, an increasingly important factor that can introduce a severe performance loss is the power supply noise. As technology advances into the nanometer regime, the operating frequencies increase, and clock gating has emerged as an effective technique to limit the power consumption in block-based designs. As a consequence, the amplitude of the supply voltage fluctuations has reached values where techniques to include the effect of power supply noise into timing analysis based on linear models are no longer adequate, and the non-linear dependence of cell delay from supply voltage must be considered. In this work we present a practical methodology that accurately takes into account the power supply noise effects in static timing analysis, which can be seamlessly included into an industrial sign-off design flow. The experimental results obtained from the timing verification of an industrial SoC design have demonstrated the effectiveness of our approach.

Keywords: POWER SUPPLY VOLTAGE; STATIC TIMING ANALYSIS; SIGN-OFF VERIFICATION; DERATING FACTORS

Document Type: Research article

DOI: 10.1166/jolpe.2006.012