Journal of Low Power Electronics

Analysis of Leakage Power Reduction in Dual-V_th Technologies in the Presence of Large Threshold Voltage Variation
pp. 1-7(7)
Authors: Wang, Wei-Shen; Liu, Michael; Orshansky, Michael

Selected Peer-reviewed Research Articles from the Patmos 2005 Workshop
pp. 8-8(1)
Authors: Vounckx, Johan; Paliouras, Vassilis

Systematic Preprocessing of Data Dependent Constructs for Embedded Systems
pp. 9-17(9)
Authors: Palkovic, Martin; Brockmeyer, Erik; Vanbroekhoven, Peter; Corporaal, Henk; Catthoor, Francky

Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications
pp. 18-26(9)
Authors: Bisdounis, Labros; Blionas, Spyridon; Macii, Enrico; Nikolaidis, Spiridon; Zafalon, Roberto

A Load-Store Queue Design Based on Predictive State Filtering
pp. 27-36(10)
Authors: Castro, Fernando; Chaver, Daniel; Pinuel, Luis; Prieto, Manuel; Huang, Michael C.; Tirado, Francisco

Back-Annotation in High-Speed Asynchronous Design
pp. 37-44(8)
Authors: Golani, Pankaj; Beerel, Peter A.

On the use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits
pp. 45-55(11)
Authors: Rios-Arambula, David; Buhrig, Aurelien; Sicard, Gilles; Renaudin, Marc

Analysis and Optimization of MPSoC Reliability
pp. 56-69(14)
Authors: Coskun, Ayse Kivilcim; Rosing, Tajana Simunic; Mihic, Kresimir; De Micheli, Giovanni; Leblebici, Yusuf

Energy-Efficient Value Based Selective Refresh for Embedded DRAMS
pp. 70-79(10)
Authors: Patel, Kimish; Macii, Enrico; Poncino, Massimo; Benini, Luca

An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits
pp. 80-86(7)
Authors: Rius, Josep; Meijer, Maurice; de Gyvez, José Pineda

Accurate Logic-Level Current Estimation for Digital CMOS Circuits
pp. 87-94(8)
Authors: Ruiz-de-Clavijo, P.; Juan-Chico, J.; Bellido, M.J.; Millán, A.; Guerrero, D.; Ostúa, E.; Viejo, J.

Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications
pp. 95-104(10)
Authors: Manet, Philippe; Ambroise, Renaud; Bol, David; Baltus, Marc; Legat, Jean-Didier

Power Supply Selective Mapping for Accurate Timing Analysis
pp. 105-112(8)
Authors: Forzan, Cristiano; Pandini, Davide; Graziano, Mariagrazia

Power – Performance Optimization for Custom Digital Circuits
pp. 113-120(8)
Authors: Zlatanovici, Radu; Nikolić, Borivoje

Transistor Sizing of Logic Gates to Maximize Input Delay Variability
pp. 121-128(8)
Authors: Raja, Tezaswi; Agrawal, Vishwani D.; Bushnell, Michael L.